1 {& s% c. o5 C 公司是美资公司，现处于高速发展阶段，计划几年内在海外上市。急聘ASIC逻辑设计工程师或项目经理与公司共同发展，前途无量。有兴趣者请联系：
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emai:
heqiu@tlsemi.com |8 F4 h+ f$ s3 |1 X: C0 S9 p5 p' M
- n4 G/ g5 ?* t* w8 CASIC逻辑设计工程师 Logic Design Engineer：
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Job Function
0 r+ J- d# K- i3 d& x! @. R7 M% JA)Design digital circuit blocks using RTL coding in mixed signal IC chips.使用RTL代码设计数字逻辑电路（用于混合信号IC）
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B)Write RTL code for custom designed blocks such as SRAM and adder blocks.编写客户定制RTL代码，例：SRAM，加法器等
' R4 A! S7 I. c; q4 i8 |C)Define micro architecture of digital part of the mixed signal IC.定义混合信号IC数字部分微架构
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D)Verification of the logic blocks using test bench and Vera.使用test bech和VERA语言
验证逻辑功能块
- I/ P5 J- s" Z t5 `- T4 M" N" eE)Use FPGA to validate the designed blocks. 使用FPGA验证设计模块
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F)Write synthesis script to generate gate level netlist.编写综合教本产生门级网表
; M" A7 `( }+ G' |9 qG)Analyze timing for synthesized blocks.分析综合模块时序
/ S7 O1 L5 E8 G+ F1 \9 l% I$ pCandidates must have the following qualifications. 申请人需有如下资格：
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A)2 years RTL coding experience2年RTL代码经验
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B)Understanding of concept of state-machine.了解状态机概念
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C)Understanding of the concept of timing. Able to perform static timing analysis.具备时序概念，能进行静态时序分析
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D)Familiar with
VCS or NC-Verilog熟悉
VCS 或 Verilog
0 Z! C; {) f' pE)Able to write and use test-bench to test RTL blocks.可以编写和使用
测试平台测试RTL模块
: B s4 H7 X0 V2 q8 [# dF)Able to program FPGA to test logic blocks.可以使用FPGA编程测试逻辑模块
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本帖最后由 猎手 于 2007-12-3 03:24 PM 编辑 ]
