急问关于spectreverilog的仿真问题
我用spectreverilog仿一个混合信号电路,模拟部分是schematic,数字部分是verilog代码
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电路已经搭好了,config也做了,IE也设好了,自己感觉设的没有问题,但是一仿真就这样:" i% X/ h9 D& _/ }
( q1 R% u8 A: j*USRERR: Net net040<3>, in module VCO_all, lib hsc_863, view schematic, R2 T4 a0 n. `, q2 E/ X8 k
requires the generation of Hierarchical Interface Element (IE) inside
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9 R( M2 P( g, g7 U, F or digital stop view set. Such an IE will be ignored by the simulator.% J9 x' W4 }8 X$ I$ U7 w
Please change your design to avoid this limitation.5 Y' |9 `2 B& y0 m/ a+ u
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我在partitioning options里面设的是:+ `' d' q6 F) I: Z& K6 f
Analog stop view list: spectre schematic( K2 K, [2 {$ P. r
digital stop view list: symbol verilog functional * K9 l N$ O2 f4 v! Q
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请求高手指点,是哪里出了问题?
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% v2 e/ V s C$ C万分感激!!!!!!!!!!!!!!!!!!!!!!!
