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1. A rule-based approach for high speed adders design verification" T& m; w+ [9 o4 V% J6 q
Elleithy, K.M.; Aref, M.A.;7 f1 l1 ?' Z' }$ d& W3 W
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
1 d8 c2 S- i/ QVolume 1, 3-5 Aug. 1994 Page(s):274 - 277 vol.1
: L* S, y6 L6 s; g- O# x: [8 uDigital Object Identifier 10.1109/MWSCAS.1994.519238 9 I- p6 i# _8 ?: F2 Z
0 G* m/ E& _, C9 N5 K$ @Summary: In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verifi.....
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AbstractPlus | Full Text: PDF(332 KB) IEEE CNF
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2. A generalized multibit recoding of two's complement binary numbers and its proof with application in multiplier implementations' S4 m3 u3 e( Y9 |- u7 P3 Z
Sam, H.; Gupta, A.;
* |) D0 F9 a2 \/ PComputers, IEEE Transactions on4 \) Z( v, J" \% d1 J
Volume 39, Issue 8, Aug. 1990 Page(s):1006 - 1015 5 X* G3 ^ q. {/ S0 g
Digital Object Identifier 10.1109/12.57039 * K9 B* \" P: p- Q5 p8 I+ o3 Z
' n/ k, d$ B; VSummary: A multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1-bit recoding will result in a signed-digit (SD) representation of the binary number in radix 2k, using digits -2
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AbstractPlus | Full Text: PDF(812 KB) IEEE JNL
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3. High performance low power low voltage adder
o+ @8 h& I4 VWu, A.; Ng, C.K.;0 ]! d6 w4 o9 }1 W( ~6 h8 _, k
Electronics Letters
% ~+ \# Z; g! g$ M4 X+ zVolume 33, Issue 8, 10 April 1997 Page(s):681 - 682
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n5 ?, B3 T* {+ H5 @: CSummary: A high performance adder has been designed for low power, low voltage applications. The proposed circuit has a better performance in terms of power consumption and area efficiency. To justify claims, simulation results of various high speed adders ar..... + J$ H8 K: ^& z9 y3 A/ ^
4 S& ]6 x" p8 J4 D7 z AbstractPlus | Full Text: PDF(236 KB) IET JNL
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* c' ^: i, G0 Y2 z: T9 V 4. Fast two's complement VLSI adder design
% C5 f3 w+ E0 c% S7 cDobson, J.M.; Blair, G.M.;7 h' O8 B" ~5 K. Z
Electronics Letters
* P8 B8 Y; f* k* |% V" I3 Y* G" O8 N1 TVolume 31, Issue 20, 28 Sept. 1995 Page(s):1721 - 1722 2 `+ a; R. M$ @2 Z
+ J- m! Y0 N$ l+ pSummary: The design by Srinivas and Parhi (1992) which used redundant-number adders for fast two's complement addition is re-examined. The underlying mechanism is revealed and improvements are presented which lead to a static-logic binary-tree carry generator.....
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2 o; ^4 Q2 V- E& X AbstractPlus | Full Text: PDF(188 KB) IET JNL : C; ]4 t: ` l4 V( V
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, w' i. ]& {7 R$ c1 T 5. A Novel Parallel Architecture of a Reconfigurable Video Processor based on Multi-radix number systems
/ v% [! S% ]) F* b4 yChatterjee, S.; Sinha, A.; Basu, D.;! m p0 `: W2 O- I
Consumer Electronics, 2006. ISCE '06. 2006 IEEE Tenth International Symposium on
$ r9 z! B* N7 D0 n$ g, m2006 Page(s):1 - 5
- t. ?0 A# o+ I9 xDigital Object Identifier 10.1109/ISCE.2006.1689434
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Summary: The potential need of the video compression algorithms is to decode a digital video bit-stream in different ways and it is likely that a number of different video representations may need to coexist in a single system thereby requiring a high degree .....
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AbstractPlus | Full Text: PDF(3637 KB) IEEE CNF
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4 \8 K& n: }( e5 E( h 6. New designs of signed multipliers; [3 U8 b" [& e+ C0 Q
Mudassir, R.; El-Razouk, H.; Abid, Z.;; w! Z+ `% `" o& p; g0 ?2 T( T
IEEE-NEWCAS Conference, 2005. The 3rd International
- R$ H- y* c/ a4 `7 r6 e19-22 June 2005 Page(s):259 - 262 . x9 C( n6 w: N i. i z- \
Digital Object Identifier 10.1109/NEWCAS.2005.1496746
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Summary: Two new architectures for signed multiplication for array and tree topologies are presented. The signed array multiplier is based on the new low power high speed adders, and achieves 15% and 30% reduction in time-delay and power consumption compared .....
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AbstractPlus | Full Text: PDF(582 KB) IEEE CNF / l f* w1 E# O- o. ?8 g
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/ h& K) `# e" Y9 ] i 7. Data dependent precharging dynamic chain architecture for low power end high speed adders
z5 i' a8 f4 g; F) [+ UWoo-Hyun Paik; In-Chul Hwang; Jae-Wan Kim; Soo-Won Kim;
9 V5 L# r' J" n% |# ^: K3 h& u J+ mASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
& k9 S/ _8 A7 D$ P2 M# \7-10 Sept. 1997 Page(s):173 - 177
1 M; y1 ^, P d/ S8 L) k0 T% qDigital Object Identifier 10.1109/ASIC.1997.617000
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( U8 \0 c9 J9 {* C& a' dSummary: This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been d.....
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# j& o0 V8 l, E) \4 R2 b AbstractPlus | Full Text: PDF(260 KB) IEEE CNF
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8. Fast addition using a new number system
% T8 ~# V9 K6 y$ c+ v/ hHashemian, R.; q+ \- D, c* j9 B7 W2 r
Signals, Systems and Computers, 1996. 1996 Conference Record of the Thirtieth Asilomar Conference on7 E% n7 F7 x2 R4 s! ^
3-6 Nov. 1996 Page(s):884 - 887 vol.2
5 U1 ]8 ^3 a; ?% T2 m1 oDigital Object Identifier 10.1109/ACSSC.1996.599071 0 y4 n8 x6 [, Q7 @0 f; U
; K2 a: d- D! J K, n8 I& w# DSummary: A new approach is proposed for the design of high speed adders. Unlike the traditional approach here the attention is on the data format. It is shown that converting one of the operands to a specific type of ternary numbers, called signed digit numbe.....
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. t) r2 [( T8 [1 Z. { AbstractPlus | Full Text: PDF(404 KB) IEEE CNF % m, b7 g. N! u
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9. Conditional-Sum Early Completion Adder Logic& e9 @1 f/ \+ @" c! ]6 P( k
Martin, N.M.; Hufnagel, S.P.;& d# v: T( S& Z1 v( Y# g
Computers, IEEE Transactions on
; L. \* L% c/ R* l/ jVolume C-29, Issue 8, Aug. 1980 Page(s):753 - 756
w; \. O- e; }0 s" hDigital Object Identifier 10.1109/TC.1980.1675663
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Summary: A high-speed parallel adder of digitally represented numbers called the conditional-sum early completion adder (CSCA) will be described. The CSCA design is based on the computation of "conditional" sums, carries, and column completion detection logic.....
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% }- g7 h- P4 T. A" e5 Q! T B3 [ AbstractPlus | Full Text: PDF(738 KB) IEEE JNL
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10. A high speed adder using Josephson elements
S: a) q& `8 mMorisue, M.; Kuramochi, K.; Matsuo, H.;) A1 a2 | r R: O/ [6 a7 @+ }
Magnetics, IEEE Transactions on/ j! r6 `8 L0 Z) m8 Y2 U
Volume 17, Issue 6, Nov 1981 Page(s):3420 - 3422 3 J2 I# ^2 h `7 X$ S \8 s
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Summary: A high-speed adder employing Josephson elements is proposed. This adder is constructed by using a novel Exclusive-OR logic and a high speed carry propagation technique. The principle of the operation is described and the simulation of the adder, of w..... # T4 G1 S, I8 ^, D5 z
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AbstractPlus | Full Text: PDF(280 KB) IEEE JNL 9 r! I9 l2 T3 w9 Q$ S) b5 \4 n' R
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11. High Speed 1-bit Bypass Adder Design for Low Precision Additions
t3 y3 S2 U I/ X [Jong-Suk Lee; Dong Sam Ha;
" I5 q. P/ m# A5 F: aCircuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on7 q) a( g2 U! C0 o0 i# B3 D
27-30 May 2007 Page(s):1093 - 1096 - W9 w" }; g d9 X2 e7 i2 ^
Digital Object Identifier 10.1109/ISCAS.2007.378200 7 H m9 Z, z( P' J% x* D& }" G
" b4 A, {+ c7 W0 a3 `7 j4 F; FSummary: In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts 8-bit processing units as the atomic operation. Hence, high speed..... ( M6 d0 A9 b& W5 n6 b, t9 m2 e
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AbstractPlus | Full Text: PDF(285 KB) IEEE CNF + `0 T2 n5 ~4 m* V
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4 G: g+ @7 i) w& S( P" ^ 12. The fastest carry lookahead adder
6 |: B& |' f2 b+ q7 tYu-Ting Pai; Yu-Kumg Chen;
% n6 [& w: n; A1 {0 z3 vElectronic Design, Test and Applications, 2004. DELTA 2004. Second IEEE International Workshop on5 G- R3 T/ G: \' J4 ?( P. {9 z
28-30 Jan. 2004 Page(s):434 - 436 ' k+ d: `/ u& ?( e/ J5 T( x3 }
Digital Object Identifier 10.1109/DELTA.2004.10071 ( G9 u) \" L; F' N+ d' E
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Summary: Adder is a very basic component in a central processing unit. The speed of compute becomes the most considerable condition for a designer. The carry lookahead adder is the highest speed adder nowadays. In this paper, a new method for modifying the ca..... - ?* V! \; Y2 s
. i" N$ l- c* Z9 U5 ? AbstractPlus | Full Text: PDF(160 KB) IEEE CNF y3 T% z, p, G3 |$ `
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1 ^ _: X. _- R6 b% ]4 a8 S* m 13. Efficient simultaneous rounding method removing sticky-bit from critical path for floating point addition+ V% g3 [6 {/ O6 R0 W/ H
Woo-Chan Park; Tack-Don Han; Shin-Dug Kim;
' r8 o, S+ p. KASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on+ ]5 E0 O. v2 E0 P) x& e7 y
28-30 Aug. 2000 Page(s):223 - 226 ; o5 M; B. Y+ g
Digital Object Identifier 10.1109/APASIC.2000.896949
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Summary: Processing flow of the conventional floating point addition/subtraction operation consists of several steps, i.e., alignment, addition/subtraction, normalization, and rounding stages in this order. A floating adder/subtractor performing addition/subt.....
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. g4 |8 ^5 W: a4 N AbstractPlus | Full Text: PDF(344 KB) IEEE CNF
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- Y) O1 o) o4 P1 y9 i: M 14. A study of a radix-2 Signed-Digital fuzzy processor using the logic oriented neural networks
' |7 [, i' P$ t( N: d. `3 W4 z- e' {+ sSakamoto, M.; Hamano, D.; Morisue, M.;
! u) \1 m7 ]- j$ DFuzzy Systems Conference Proceedings, 1999. FUZZ-IEEE '99. 1999 IEEE International
) Q: O9 V7 y/ s5 o" ~# u) t% e0 {Volume 1, 22-25 Aug. 1999 Page(s):304 - 308 vol.1 1 f" X9 ~' j6 l, w; w8 E- J
Digital Object Identifier 10.1109/FUZZY.1999.793255
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Summary: A novel Signed-Digital fuzzy processor using the logic oriented neural networks is proposed. Since the signed-digit number system has a redundant property to represent the binary numbers, the high speed adder in the processor can be realized in the s..... 3 j4 R6 s$ v$ J0 h9 m# }3 ~
; C3 o% \5 [0 b4 N; z# H2 ]" C5 ^ AbstractPlus | Full Text: PDF(308 KB) IEEE CNF / D; M1 A) _. W
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15. Quantitative simulation of strained and unstrained InP-based resonant tunneling diodes
5 |8 P) z1 O0 w$ S4 i; VKlimeck, G.; Boykin, T.B.; Bowen, R.C.; Lake, R.; Blanks, D.; Moise, T.; Yung-Chung Kao; Frensley, W.R.;
( y \+ S" U* Y& ADevice Research Conference Digest, 1997. 55th% v# |: A% {" N+ r( x- @
23-25 June 1997 Page(s):92 - 93
# z$ J/ b5 U( }Digital Object Identifier 10.1109/DRC.1997.612487 1 V/ _; c4 u1 m+ E/ b6 U
u, G: }8 I1 B, e& J" V! XSummary: State-of-the-art InP-based resonant tunneling diodes (RTDs) are being developed for circuit applications such as low power memory cells and high speed adders. Depending on the application RTDs must be designed to provide either a low or a high curren..... , \. U! K& m1 h& D/ D
5 x) }9 ?; j( Z0 P7 d1 M* S$ X AbstractPlus | Full Text: PDF(184 KB) IEEE CNF
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16. High Speed Adder Circuit Using Dummy Carry method! N: z! Y4 t' g+ Q/ O3 w' C- G
Mori, J.; Kondo, Y.; Ikumi, N.;) g; X% l8 ^& C7 H' i, J0 h
VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on2 f0 b" E* }3 R- z6 \
June 12-14, 1997 Page(s):39 - 40
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Summary: Not available..... ' w& }2 v; y d9 P$ i% \. q
7 t* w+ I3 F# l; L3 H( C AbstractPlus | Full Text: PDF(212 KB) IEEE CNF / c- F) N% i8 X' f
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17. A new self-checking code-disjoint carry-skip adder
4 ^$ d; o9 V; ]7 ~% Y& ]Marienfeld, D.; Sogomonyan, E.S.; Ocheretnij, V.; Gossel, M.;& K$ [% _/ q% i# n
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
/ y9 y. B6 ]5 G) D/ H8-10 July 2002 Page(s):39 - 43 & L* a2 N W* V
Digital Object Identifier 10.1109/OLT.2002.1030181 6 n" P; M, U- o% f, q8 V
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Summary: In this paper the first self-checking code-disjoint carry-skip adder is investigated The adder is code-disjoint with respect to the parity encoded operands and self-testing and fault-secure with respect to all single stuck-at faults of the adder cell..... 1 g' z7 ?* `/ m0 o# _. |) [
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AbstractPlus | Full Text: PDF(280 KB) IEEE CNF ; O5 c [9 c. ?, D( @' \$ L- @2 i
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18. High-speed low-power adder with a new logic style: pseudo dynamic logic (SDL)
$ X5 S* q6 T, j- ZChaji, G.R.; Fakhraie, S.M.; Smith, K.C.;7 `$ _9 o& D, \9 M, _* i
Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on
; _- q, M8 |+ v& R3 G29-31 Oct. 2001 Page(s):137 - 140 + P* }* S5 L' k( u' Z; U
; ^7 z0 x ]( V$ b6 _Summary: In this paper, a high speed and low power adder is designed using a new logic-design style called Pseudo Dynamic Logic (SDL). Traditional dynamic logic is pre-charged to a default value and in the evaluation phase is changed to its real logic, Howeve.....
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$ c" I3 N4 f" V% f AbstractPlus | Full Text: PDF(348 KB) IEEE CNF
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' D- s( p4 y5 u$ |" r 19. A compact adaptive equalizer IC for HIPERLAN system
2 x' f9 ? Q% I- V8 F, }- |Jinn-Shyan Wang; Pei-Lung Lin; Wern-Ho Sheen; Duo Sheng; Yu-Ming Huang;
" E! ^' P5 n! o0 J5 [8 A JCircuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on1 x1 l1 \6 W; I8 e/ }, f
Volume 2, 28-31 May 2000 Page(s):265 - 268 vol.2 % r6 q5 ~) g. \* s/ Z
Digital Object Identifier 10.1109/ISCAS.2000.856312
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Summary: The design of a compact high-symbol-rate adaptive equalizer IC for the receiver of a high-speed local area network that meets the ETSI HIPERLAN standard is presented in this paper. Although the HIPERLAN defines a slowly time-varying multi-path fading..... , t1 z( e9 ~$ `7 G
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AbstractPlus | Full Text: PDF(360 KB) IEEE CNF
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20. Testability synthesis for jumping carry adder1 I, p- T7 h9 u! m) z& X! ]
Wagh, M.; Chen, C.-I.H.;
% t: o+ q; E; m5 C P' uASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International; Z0 d- L! k8 ^7 J' J, v) Y
15-18 Sept. 1999 Page(s):130 - 134 . z6 X% j, b% J( `) E- A
Digital Object Identifier 10.1109/ASIC.1999.806490
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Summary: Synthesis for testability process ensures that the design is testable, which exploits the fundamental relationships between don't care and redundancy in combinational and sequential circuits. In this paper a testability synthesis with redundancy remo.....
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AbstractPlus | Full Text: PDF(264 KB) IEEE CNF ( b' R/ r, T) b" y; t- U1 X
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1 a9 G: ~, B8 j- O2 w B9 \- c; {; n; x 21. A new cell for low power adders2 Q* x \" J( I- x. b
Abu-Shama, E.; Bayoumi, M.;! v0 N- S: Q) _
Circuits and Systems, 1996. ISCAS '96., 'Connecting the World'., 1996 IEEE International Symposium on, a6 J' O: A; }: C: R
Volume 4, 12-15 May 1996 Page(s):49 - 52 vol.4
, ^$ B8 d$ `9 I: hDigital Object Identifier 10.1109/ISCAS.1996.541898 * x- W! y# b: M+ f# c; p
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Summary: Reducing power dissipation at the circuit level is considered one of the main factors in developing low power systems. Also, minimizing power of the most commonly used circuit module, will lead to a global power reduction. Following these two design .....
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AbstractPlus | Full Text: PDF(256 KB) IEEE CNF
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With your idea, Carry out together.
