A. General
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- k/ n2 \4 x0 d6 cA.1 什么是Verilog的PLI?
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9 e0 A# u" m5 W$ }可编程语言接口(PLI) is a mechanism to interface Verilog programs with programs written in C language. It also provides mechanism to access internal databases of the simulator from the C program.
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" M$ P2 G) w' O7 _. SA.2 Why is it used for ?
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PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and hardware related features of Verilog and sequential flow of C - using PLI.
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& I' \& t; w7 p% j: @" D* p% t& mA.3 Verilog PLI应用最频繁的是什么？
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PLI最通用的应用的是延时反标，编写延时计算器和开发用户界面。
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% ~4 Q# Y9 s$ ~( MA.4 等等，等等。我是一个VHDL用户，已经impressed。有没有VHDL PLI？
1 G3 s* u$ r+ V v8 A( r( E7 lVHDL does not have a PLI (one more reason for you to switch to Verilog), although preliminary proposals are there for standardizing such an interface.
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" a. Y8 U9 m5 C( D( }, H/ YA.5 Gee! Is there anything that PLI does NOT allow ?
8 K! v- i0 G* {6 J( X; D3 {; e$ d3 wVerilog PLI does not permit anything goes against the rules of the language. You can not, for instance, assign a value to a wire, just as you can not do that in Verilog program either. Apart from these, there are few things that Verilog PLI does not allow; most notable among them are : you can not create an object and you do not have access to compiler directives (although, in most cases you can see their effects).
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2 p( V/ t6 l- n4 uA.6 I heard PLI applications slow down the simulation and make the simulation environment clumsy ?
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Alice: "Mr. Rabbit, can you tell me where does this road go ?"
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Mr. Rabbit: "That depends on where you want to go."
+ m& J. c# \# FWe have been asked this question several times. Over the years, we figured out there is no definite answer to this question as there is no clear benchmark available. We will also explain why the question itself is not well-defined below. The above question usually takes two forms. First, if I write a PLI application and use it in my simulation, does that slow down the simulation ? The answer is of course yes , just as any other added code would do in any other programming language. However, if you do not use the PLI application in your Verilog model, the answer depends on a lot what the application does and which simulator you use. See for example, this answer .
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The second variation is if I write a C model and then use PLI to integrate it with main Verilog source, will that be faster than the corresponding Verilog model ? Here also it depends on which simulator you are using and what your model does. This is an answer from one of the Verilog simulator vendors.
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Having said that, for most of the applications that we have seen, our emperical judgement is that any simulation performance degradation due to PLI is not that big as long as the applications themselves are well-written and do not violate basic programming rules.
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T# K7 u$ X5 X" GB.资源 + G' Q s9 Q" N H F. X3 T
' k& Q+ }: L7 Q% wB.1 有没有有关Verilog PLI的书？
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4 v2 g; ~+ \- E' S D- _! T2本有关 Verilog PLI的书。
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Principles of Verilog PLI
0 m' N7 [$ ]; f# Q& cSwapnajit Mittra
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Kluwer Academic Publishers, Norwell MA
) T4 Z" z9 S/ Y: B8 ?8 @9 OISBN: 0-7923-8477-6
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( |' m" J }1 f0 ^Using the Verilog PLI: A Tutorial and Reference
: a: i2 q/ x9 O1 lStuart Sutherland
0 r' m- Y. D1 k$ {Kluwer Academic Publishers, Norwell MA
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其他的Verilog PLI资源有2个标准手册。
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IEEE Std 1364-1995 : IEEE Standard Hardware Description Language based on the Verilog Hardware Description Language
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Published by the IEEE, Inc., 345 East 47th Street, New York, NY 10017, USA
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ISBN 1-55937-727-5
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9 U! z0 O7 s9 {" t, `OPEN VERILOG INTERNATIONAL (OVI) PROGRAMMING LANGUAGE INTERFACE (PLI), Version 2.0
( }' ]" i- s' w. i$150 per copy, plus local sales tax
$ a+ j$ I5 Z' G2 q, g4 HOpen Verilog International
" o# v: d! B8 a0 \5 u# zLynn Horobin
% J: _2 o, J6 [. a" Y15466 Los Gatos Blvd., Suite 109-071
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Los Gatos, CA 95032
+ x, ~# l3 h$ t3 w( m4 fPhone: (408) 353-8899 -- FAX: (408) 353-8869
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ovi@netcom.com : {! ^, Q1 n+ H
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7 {/ `" y5 l- Y8 FB.2有没有关于PLI的网站?
( M* U' E1 Y; o: ]4 ^Well, you are reading one right now.
% g+ C0 s3 J" Y! n. h* MApart from this, here is an incomplete list:
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A Brief Introduction to PLI
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C. Preparations 1 B7 e5 N7 b! h( W5 H, Q& |" i
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; z; p; u/ Y' fC.1 I do not know C. Can I write a PLI application in any other language than C ?
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3 C% V. f; S! wThe answer to this question is "Yes" and "No". If you are not accessing design database (for example, if all that your program does is "Hello! World."), you can write it in any language, compile it to object code and link it to Verilog and other PLI C programs. However, if you are accessing the database (e.g. reading/writing some register etc.) you do not have much choice than to use C. This is because libraries have language bindings.
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Notice that, some simulators do support C++. The process of linking a C++ routine to these simulators varies. You need to look at the manuals of these simulators to find out how exactly the process works. See C.7 and C.8 for more details on this subject.
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+ K0 E2 Y' x$ q5 T+ e" \C.2 Why do not I see a main() in a PLI application ?
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Because, your PLI routine is not an independent C program. It consists of C functions which are called by the actual main() function of the simulator (or one of its sub functions).
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; M1 w, c3 F/ m8 P3 O5 }C.3 What are s_tfcell and veriusertfs[] ?
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s_tfcell is a predefined data structure defined as a structure to hold, among things, the type of the PLI routine (task or function) and names of the component functions. veriusertfs[] is an array of these structures.
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VCS and there is no such data structure as s_tfcell and veriusertfs[] in it. Why ?
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This is because VCS uses a file with the equivalent data in it. This file is normally called a table file.
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C.5 I saw veriuser.h as part of IEEE Std. 1364-1995. But my VCS distribution does not have it. What's wrong ?
6 L/ ?: Z( Y# U+ MVCS uses its own header file called vcsuser.h.
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3 E4 f. P, l7 u$ g) C8 }( yC.6 What is a callback ?
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A callback is a mechanism to invoke a function when some other event occurs.
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6 P! T' w; ]% a4 r+ y) EC.7 Can I write my PLI application in C++ ?
0 |& s* H" ~) J" iOne of the most favorite questions from our readers. The short answer is "Yes, in most cases". Click here for a longer one.
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; S8 } ^% M4 {1 O2 T/ z7 `, gC.8 Can I write my PLI application in Java ?
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There are two known interfaces between Verilog and Java.
# h7 M3 T& `5 tTime-rover Inc. sells a Java PLI interface enabling you to access the entire Java suite of packages. Click here to reach their website.
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Newisys has released Jove, an open verification environment for the Java platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language.
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C.9 Can I write my PLI application in Perl/Python ?
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There are at least 3 programs that support Perl interface to Verilog PLI. Two of them also support Python interface. Wilson Snyder has dedicated his Perl package Verilog_pli to the Verilog user community. It is available from his VeriPool webpage. A student project in Berkely named ScriptEDA has a Perl/Python interface. Lastly, NelSim Software provides an open source package that can be downloaded from their ScriptSim page. According to Nelsim, "ScriptSim does not involve linking an interpreter into the simulation. The interpreter runs outside the simulation, making it impossible for script errors to crash the simulator. It also allows the interpreter to create sophisticated GUIs without interfering with the simulation."
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$ Z9 Q) I5 R2 Y! c+ z* }/ u5 iD. Compilation
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D.1 Does it matter if I use a 16 bit, 32 bit or 64 bit C compiler for compiling my application ?
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) o. s* ^, D0 f- }0 J) @No. Internal variables of the simulators are independent of system specification. For example, integer is assumed to be 32 bit irrespective of whatever system you are using.
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D.2 During compilation, I get an error message
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ld: Unresolved symbol: tf_...
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Probably you forgot to include veriuser.h or one of its variants.
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. w8 E. d7 \' R5 r0 u: B1 t3 nD.3 During compilation, I get an error message
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handle myHndl;
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Syntax error: at or near symbol myHndl
7 u; I3 n3 F9 w8 ~Probably you forgot to include acc_user.h .
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D.4 During compilation, I am trying to port an application which was earlier used with Verilog-XL/NC, but during compilation I get the following error message:
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vpi_user.h - include file not found.
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Either you have not set the path correctly or you are trying to compile the application in an environment which does not support PLI2.0.
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$ \2 s6 A# [. O& `7 t7 SE. Libraries/Versions
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! ~/ Y- O# j' C2 H: v, X+ ^E.1 Given a choice, which of the three types of routines - TF, ACC and VPI - should I use for my application ?
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It depends on a number of factors, including the nature of the application that you are writing and your own familiarity with the libraries. If the nature of the application allows you to use any of the three functions, it seems TF routines are faster.
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E.2 Can I use libraries from both versions of PLI in the same application ?
% C5 N3 _! G$ K1 z0 c \5 LYes, as long as you are including the right header files.
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E.3 Are "handle"s interchangeable between PLI versions 1.0 and 2.0?
& v" m9 X/ \4 ^% ^Handles in PLI1.0 and 2.0 are of different types. The data type for PLI1.0 handle is handle, when the data type for 2.0 is vpi_handle. So, they can not be used interchangeably. However, Cadence Design Systems in its implementation of PLI2.0, provides two functions for converting handles from one type to the other.
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F. How do I ...? ; G7 K8 L6 Z) }; I, H
# q! F8 k! ~6 i0 ^4 z* T) { i, GF.1 如何从用户定义函数中返回值？
n7 {* O; G, \6 k; v, N$ u使用tf_putp()或者 tf_strdelputp() 自变量 0, i.e.
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tf_putp(0, ret_val);
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$ e% Z$ X9 f! @8 ^F.2 什么库函数可以读取寄存器的值呢？
# j, \6 _* m$ H9 ^( L) p, w3 xtf_getp() or tf_strgetp().
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! H) T6 q) @- v$ S. S' m0 a0 MF.3 什么库函数可以写入寄存器？
8 N' \) F5 f! N# m8 ltf_putp() or tf_strdelputp().
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) ~( J& d" j- F/ U; xF.4 什么库函数可以读取存储单元的值？
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tf_nodeinfo().
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F.5 Is there an access routine to manipulate memory variables in Verilog PLI ?
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Not in the standard Verilog. VCS is working on providing one in version5.1
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) B) [9 a2 _( ], f4 s. NF.6 How do I change delay value of an object ?
1 u @6 T2 } X" P- I) ZIf you want to add a value to an already existing delay value, use acc_fetch_delay(). If you want to replace the current delay value with a new one, use acc_replace_delays().
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+ H) O! I G, p$ v9 N& `7 }F.7 How do I implement a callback ?
. u' ^. f( G" a/ `" h+ X* |There are different kinds of callbacks and depending on what kind you want to implement as well as what version of PLI you are using, you need to use different library functions. For example, in PLI1.0 you need to use the function tf_setdelay() for introducing a callback event after certain simulation time, tf_asynchon() to invoke a function asynchronously whenever any parameter value changes.
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F.8 Is there a PLI library function to tell me the value of a macro (defined using `define) ?
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No. Macros are preprocessed and substituted before the actual compilation takes place. So it is not possible for a PLI routine to find out the value.
6 D$ R, u$ M3 A8 c2 qA trick to avoid this problem is to define the macro as an environment variable before running the simulation, then inside your PLI routine use the standard C library function getenv() to access the value of that environment variable. If you intend to change/undefine the macro, use another PLI routine which calls putenv() to set a new value of the variable.
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: y) K8 f" }( \7 H: t; EF.9 PLI C/C++程序能否调用verilog任务和函数？
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A C/C++ function in a PLI application can not invoke a Verilog task or function directly. But, here is a work-around for that.
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1.声明一个 reg:
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reg flag;" K. T3 B$ j8 ^( z
initial flag = 1'b0;. S: C' J4 r! w( E1 C3 E
2. 把这个reg和其他自变量一起传递给
系统调用:
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$ `+ e9 k, S, D5 d' ?! {5 C4 J; u $my_call(flag, ...);
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3. 在PLI程序内改变这个reg值，在你想调用Verilog任务和函数的时候。
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tf_putp(1, 1-tf_getp(1));9 T3 ~) I: ~% J
4. 回到verilog语言, 加上这个
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3 v& N$ G: r1 K call_my_task(...);
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当flag改变这个值时，这将调用verilog任务 call_my_task()。
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1. 若出现类似于以下错误代码，怎么办？
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ncsim: *internal* (sv_seghandler - trapno -1).
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Observed simulation time : 18525 NS + 0
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Please contact Cadence Design Systems about this problem
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***Current stack trace:
) h3 V# e1 T k$ R, ]0 w-->[User Code ] 0xb6b316ec input_mon + 60 ../pli/mon/input_mon.so
7 a+ v) h5 o+ m; }5 J, u! @1 Q4 i-->[TF CB Support ] 0x811531f <don't know>
( {* T( b0 e. g-->[VPI Overhead ] 0x8148cca <don't know>
8 p( @8 g8 M! e+ d0 D& O" @& z***Verilog source where error occurs:
" E6 Q8 R, B6 S' J& t6 \1 n' T $input_mon(...) (PLI calltf)
/ a, K# d' E2 f Module: input_mon
. |3 R9 ?9 v. I* Q/ { _ Instance: tb.input_mon
( F* c" ^) K9 H/ @5 C* g File: ../pli/mon/input_mon.v
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6 W$ g; M \4 E9 e. Q8 c$ tncverilog: *E,SIMERR: Error during Simulation (status 1), exiting.
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% G5 N1 x' H) h( A答： 应该是C代码有问题。检查C代码。
