The decision to use a full scan or partial scan methodology has a significant impact on DFT design. How to select in project? Anyone can give some suggestion?

little experience： when the chip have simple clock strategy，u can switch the all the clock to a main test clock for full scan。 when the chip have complex clock strategy or have hard IP core which have it's own test chain ，u will select serial partial scan chain for different part or different clock domain。 for the full scan chain it work simply，it is the first choice 。 in our design ，the chip have ARM9 and ZSP500 hard core，will set three scan chain，one for ARM9，one for ZSP500，the last for the rest part of the design which have serveral clock domain。 it hard to set two or more clock domain DFF to one scan chain ，for the timing skew 。 the perfect scan chain is that less test pattern can test the most of the manufactory faults。 The cost of test depends the test timing of the chip on ATM and is expensive。

Exactly! i agree [s:4]

我靠 ，all english

ahan,could u leave your qq number for me ,i want to communicate more with u,and learn more from u,now i am learning the DFT,thank you My qq: 87510217

又学到东西了！！ 感谢斑竹！

基本搞明白了，但是还有些地方不是很清楚