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http://spaces.msn.com/EastDragon ... LAnZnHzLA!114.entry
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How does a data-to-data check perform a setup check?
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----------------------------------------------------
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6 s2 R& u2 ~ X( f* lQuestion:
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I have two data paths from register1 and register2 Q pins: one through a buffer
- L4 A* i6 q6 M: H* D+ P+ }and one through an inverter. They reach an OR gate A and B pins. I use a
$ T4 C2 Q) ^! R6 x( \data-to-data check in PrimeTime to check the timing between them. However, the
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edge relationship showed in the report_timing report seems incorrect. It is
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supposed to be a zero-cycle check. In other words, it should check the capture
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edge with the closest previous launch edge. But PrimeTime seems to check the
5 J. e5 _; k: }( C/ P7 C3 \capture edge with closest NEXT launch edge. It seems to not make any sense in
2 N" ]$ S3 ~* u! F5 ]4 a2 Ia setup check. Please explain.
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7 e0 o) A) J2 I& xVerilog file:
2 _$ U) x; t: A$ Q) gmodule test(A,B,d_clk,clk,OT);
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input A,d_clk,clk,B;
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output OT;
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FD1 my_reg1 (.D(A), .CP(d_clk), .Q(n1));
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IV my_inv (.A(n1), .Z(n2));
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IBUF1 my_buf (.A(b1), .Z(n3));
/ b1 V3 X" l4 d* {% h6 V- hOR2 my_gate (.A(n2), .B(n3), .Z(OT));
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FD1 my_reg2 (.D(B), .CP(clk), .Q(b1));
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endmodule
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0 Y' l# r: t# J" @Script file :
- C! R: o$ [, @# c0 Y' \read_verilog test.v
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/ E6 J, o1 P% \. Y8 m t1 hcreate_clock -p 20 -w {0 10} d_clk
9 i5 C. Q! O6 mcreate_clock -p 20 -w {5 15} clk
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set_data_check -rise_from my_gate/B -to my_gate/A -setup 0.66
+ u; f9 V: I- qreport_timing -delay max -to my_gate/A
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Timing report :
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Startpoint: my_reg1 (rising edge-triggered flip-flop clocked by d_clk)
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Endpoint: my_gate (rising edge-triggered data to data check clocked by clk)
1 y9 ~+ d k9 W+ g9 }Path Group: clk
- \) A$ i) y5 Z8 PPath Type: max
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Point Incr Path
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---------------------------------------------------------------
: J' x( b' a9 R0 |; wclock d_clk (rise edge) 20.00 20.00
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clock network delay (ideal) 0.00 20.00
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my_reg1/CP (FD1) 0.00 20.00 r
6 ^% B! Z! X& g! O1 I; Omy_reg1/Q (FD1) 1.44 21.44 f
& K1 P! y9 ]) m7 G# ~" y4 Lmy_inv/Z (IV) 0.58 22.02 r
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my_gate/A (OR2) 0.00 22.02 r
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data arrival time 22.02
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clock clk (rise edge) 5.00 5.00
, [7 {6 u& }3 ^clock network delay (ideal) 0.00 5.00
2 w- W* _, ]# [) kmy_reg2/CP (FD1) 0.00 5.00 r
$ C9 F* Y, ~( }# mmy_reg2/Q (FD1) 1.29 6.29 r
; N% c- Z" Y# Z! {% y% d, N" j rmy_buf/Z (IBUF1) 0.68 6.97 r
( \/ l# X' j# Qmy_gate/B (OR2) 0.00 6.97 r
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my_gate/B (OR2) 6.97 r
8 q, U) p0 {5 w) x% Slibrary setup time -0.66 6.31
" [: U3 y& a3 {+ B5 P) O6 Odata required time 6.31
. n% S6 Q% S2 u; x---------------------------------------------------------------
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data required time 6.31
( ]1 K$ d& q0 B9 @3 i" Hdata arrival time -22.02
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! g& e7 k6 S8 K, j, ^1 r" `8 oAnswer:
1 N6 e+ |2 o% tThe selected setup edges are correct and as expected. The edge selection for
1 D0 F) j# k1 e/ X& Sdata checks follows the same principles as path-based setup/hold analysis in
; f+ ] Q6 x# }4 r& }PrimeTime, except that by default the check is zero cycles. Setup checks as
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in this case, for a 1-cycle relation, are from the capture edge to the
; \# y! J5 P9 }, Jtightest previous launch edge:
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& S0 v) s( q# `- x! W7 |1-cycle setup = d_clk at 0 -> clk at 5
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The zero cycle check is (1-cycle check - 1 period of the capture clock)
$ |+ D. Z$ K# b0 S) }Subtraction in this context implies moving the capture edge 1 period back
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in time.
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0-cycle setup = d_clk at 0 -> clk at -15
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If we expand the by the base period it results in
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9 a7 k- e1 A" n: |0 l = d_clk at 20 -> clk at 5
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$ v- E/ F U/ C9 g6 M8 {) T/ q0 C! m0 QTo modify these relations, use set_multicycle path ON THE CONSTRAINED PATH
- X1 R0 F( U3 [7 M6 h(in this case, the path to my_gate/A) with the appropriate relation.
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set_multicycle_path 1 -to my_gate/A
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$ e5 Y9 L4 ]4 x3 Z6 t6 aThis is the timing report after setting the multicycle_path:
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Startpoint: my_reg1 (rising edge-triggered flip-flop clocked by d_clk)
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Endpoint: my_gate (rising edge-triggered data to data check clocked by clk)
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Path Type: max
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Point Incr Path
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clock d_clk (rise edge) 0.00 0.00
1 B; M* Y" b. Y) ^clock network delay (ideal) 0.00 0.00
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my_reg1/CP (FD1) 0.00 0.00 r
$ F, X+ n+ E- k% Emy_reg1/Q (FD1) 1.44 1.44 f
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my_inv/Z (IV) 0.58 2.02 r
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my_gate/A (OR2) 0.00 2.02 r
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data arrival time 2.02
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clock clk (rise edge) 5.00 5.00
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my_reg2/CP (FD1) 0.00 5.00 r
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my_reg2/Q (FD1) 1.29 6.29 r
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my_buf/Z (IBUF1) 0.68 6.97 r
/ T3 d. }1 h6 ?( |; ~my_gate/B (OR2) 0.00 6.97 r
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my_gate/B (OR2) 6.97 r
X, o8 C+ W) d4 w% Wlibrary setup time -0.66 6.31
% B H% P8 \' K+ @data required time 6.31
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---------------------------------------------------------------
4 Z P5 {) m. [: T& A+ @ ddata required time 6.31
1 \' b( ^- ^5 udata arrival time -2.02
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---------------------------------------------------------------
( K8 t8 ^0 \% A6 T9 F) vslack (MET) 4.29
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Note: Currently the multicyle path applies to both the data-check constrained
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path and the full path. An Enhancement Request (STAR 147028) has been made so
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that a multicycle path can be applied only to the data-check constrained path
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without applying it to the full path.
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% \; x; ?& X+ ~9 q' F##################################
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if you want to get the detailed file, contact with me via
EastDragonInc@hotmail.com
