soc design flow(one type): system spec-->code design + ip -->function verification + debug --> fpga verification -->dft-->synthesis-->STA,fm verification -->place-->CTS,route-->STA-->post simulation,fm verification-->sign-off (tape out)

fm 是firmware吗? 位置有点奇怪

fm 是firmware吗? 位置有点奇怪

no, it's formality for formal verification what does firmware mean? tool or flow? can u explain it? 3q

dft-->synthesis-->STA? synthesis-----dft----STA?

in the book <<Advanced ASIC Chip Synthesis _DesignCompiler&Primetime>>the segment should be : -->syn, dft -->STA-->

firmware 是SOC中的软体

我查了一下，好像firmware是固化的SOFT CODE，一般存在ROM里面。楼上说的对

fireware refer to compile code or driver for the mcu or dsp.

synthesis should be done before dft

ahan讲的对，呵呵，没有门级的电路，扫描链是没法插入的

back-end,用STA 验证时序，FM验证功能， 在tapeout前，用gate leve simulation 再验证一次功能和时序？ 最后physical verification(DRC, LVS, ERC)对吗？ front-end, 用simulation 验证功能(CBS,EBS), 也许还有property checking.?

楼上说的对，只是都是说了一部分。呵呵

now synthesis & dft & low power design are done together...not seperated generally...

For your design step, you should take your design dfts/low power  control.., the dft & low power tools only implement your ideas...

most of some related dft & low poewr designs are included in RTL codes.